The trend to continue to miniaturize semiconductor integrated circuits to achieve submicron feature sizes and increase the number of devices fabricated on the integrated circuit has required faster downscaling of lateral dimension than vertical dimensions, resulting in larger aspect ratios in surface topography. With densely packed circuits, there is a need to isolate components which are adjacent to each other to prevent leakage current. As with MOS transistors, current flows along the surface between the source and drain. The MOS transistors formed adjacent to each other must be separated by an isolation film thick enough so that there is no field induced current flowing under the film. Isolating adjacent components in such a manner as to minimize surface topography is known as isoplanar isolation.
Before the introduction of local oxidation of silicon (LOCOS) processes, it was common to provide MOS field isolation by growing a thick layer of field oxide across the wafer, then masking and removing oxide where active areas were to be formed. Using a wet etch step, this process did not allow for the creation of vertical oxide sidewalls. However, potential step coverage problems were avoided with this process, but at the expense of layout space, thus limiting device performance.
The introduction of LOCOS was a great technological improvement. However, several problems occurred with LOCOS. Non-uniform thermal oxidation of a wafer surface, in the original LOCOS form, always incurred lateral encroachment, or tapering of the field oxide in the active areas growing under a nitride mask. This tapering effect, called "birdbeaking", is a sacrifice of active area that becomes significant for feature sizes less than 1.5 microns. Attempts to suppress birdbeaking caused stress-related defects in the nearby substrate. Process complexity then occurred in attempting to avoid these stress-related defects.
To achieve submicron geometries, there can be little or no physical loss of the active areas as occurs with the birdbeaking phenomenon. Thus, it is necessary to reconsider the prior art approach where vertical walls are needed to manufacture devices with feature sizes less than 1.5 microns. Abrupt topography results from vertical walls, causing difficulty in subsequent patterning and etching of films deposited over the wafer. Moreover, vertical walls, or near vertical walls, can only be achieved by dry etching of oxide. Damage to the active areas may result from marginal overetching.
For a number of years, various observers have noticed the potential value of selective epitaxial refill of contact holes etched through field oxide in order to achieve a completely planar surface. Selective epitaxial refill may cause defects near the active area/field oxide interface because the epitaxial layer is unable to grow in the (111) direction. Anomalies in epitaxial growth may also result due to any etching damage of the starting surface before the epitaxial refill.
It would be desirable for a semiconductor process to produce isoplanar isolated active and field regions.
It is a further object of this invention to provide such a semiconductor fabrication process by anodizing and oxidizing the field oxide regions and refilling the remaining areas with epitaxial silicon.
It is yet another object of this invention to provide such a semiconductor fabrication process for making isoplanar active regions separated by isoplanar field oxide isolated regions which are suitable for use with small device geometries.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with its drawings.